{"id":1447,"date":"2015-09-21T14:21:28","date_gmt":"2015-09-21T19:21:28","guid":{"rendered":"http:\/\/jungwon.kim\/blog\/?p=1447"},"modified":"2015-09-21T14:21:28","modified_gmt":"2015-09-21T19:21:28","slug":"intels-hpc-scalable-system-framework","status":"publish","type":"post","link":"https:\/\/blog.jungwon.kim\/?p=1447","title":{"rendered":"Intel&#8217;s HPC Scalable System Framework"},"content":{"rendered":"<p><a href=\"http:\/\/www.intel.com\/content\/www\/us\/en\/high-performance-computing\/hpc-scalable-system-framework.html\">http:\/\/www.intel.com\/content\/www\/us\/en\/high-performance-computing\/hpc-scalable-system-framework.html<\/a><\/p>\n<p>&nbsp;<\/p>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Scalability\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-scalability-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-scalability-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Scalability\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Scalability<\/h3>\n<p>Delivering new dimensions of scalability, from workstations and clusters to the world&#8217;s largest supercomputers.<\/p>\n<\/div>\n<\/div>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Flexibility\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-flexibility-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-flexibility-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Flexibility\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Flexibility<\/h3>\n<p>Designed for both compute-intensive as well as data-intensive application requirements.<\/p>\n<\/div>\n<\/div>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Balance\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/icons\/rwd\/diecon-working-together-gears-ko-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/icons\/rwd\/diecon-working-together-gears-ko-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Balance\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Balance<\/h3>\n<p>Providing unprecedented levels of integration helps to ensure CPU, memory, I\/O, and storage all work in harmony.<\/p>\n<\/div>\n<\/div>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Improved Bandwidth and Reduced Latency\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-bandwidth-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-bandwidth-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Improved Bandwidth and Reduced Latency\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Improved Bandwidth and Reduced Latency<\/h3>\n<p>Moving all the HPC building blocks closer to the processor greatly shortens the distance data must travel, improves bandwidth, and reduces latency.<\/p>\n<\/div>\n<\/div>\n<p>&nbsp;<\/p>\n<div class=\"clearfix visible-lg\"><\/div>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Integration\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-integration-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-integration-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Integration\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Integration<\/h3>\n<p>Integrating the fabric interface and memory into Intel\u00c2\u00ae processors enables reduced power, improved performance, and greater reliability.<\/p>\n<\/div>\n<\/div>\n<div class=\"blade-item col-xs-12 col-ms-6 col-sm-4 col-md-3 col-xl-2\">\n<figure class=\"blade-image\"><span data-alt=\"Application and Performance Portability\" data-picture=\"\"><span data-src=\"\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-legacy-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" data-onerror=\"\/etc\/designs\/intel\/global\/white.png\" data-media=\"(min-width: 1200px)\"><img decoding=\"async\" src=\"http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/images\/illustrations\/RWD\/aurora-icons-legacy-blue-trn-rwd.png\/_jcr_content\/renditions\/intel.web.320.180.png\" alt=\"Application and Performance Portability\" \/><\/span><\/span><\/figure>\n<div class=\"blade-item-content\">\n<h3>Application and Performance Portability<\/h3>\n<p>Preserve your investment in legacy software and coding expertise.<\/p>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>http:\/\/www.intel.com\/content\/www\/us\/en\/high-performance-computing\/hpc-scalable-system-framework.html &nbsp; Scalability Delivering new dimensions of scalability, from workstations and clusters to the world&#8217;s largest supercomputers. Flexibility Designed for both compute-intensive as well as data-intensive application requirements. Balance Providing unprecedented levels of integration helps to ensure CPU, memory, I\/O,<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[4],"tags":[],"class_list":["post-1447","post","type-post","status-publish","format-standard","hentry","category-cs"],"_links":{"self":[{"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=\/wp\/v2\/posts\/1447","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1447"}],"version-history":[{"count":0,"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=\/wp\/v2\/posts\/1447\/revisions"}],"wp:attachment":[{"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1447"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1447"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.jungwon.kim\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1447"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}